The present invention generally relates to a video image signal decoding method and apparatus for decoding a plurality of decoded video image signals simultaneously.
Conventionally, in the system for transmitting the moving picture or the audio such as the television broadcast, the television conference system or the television telephone, or the system for recording the moving picture or the audio signal in the magnetic disc, the optical disc or the magnetic tape, and for reproducing the recorded signal, the high efficiency coding is performed then the transmission efficiency enhanced, in order to use the transmission channel or the recording medium effectively.
Also in recent years, a digital satellite broadcast via a broadcast satellite or communications satellite starts in order to solve the channel insufficiency of the analog ground wave television broadcasts or to develop new multi-channel services. Also, there are moves of digitizing the cable television (CATV) transmitted through a communication channel of coaxial cables or optical fiber cables or the ground wave broadcast.
Since in the digital broadcast the digitized video image signal or audio signal are high efficiency compressed through the use of the compression technique such as the MPEG system or the AC-3 system it is possible to secure channels by six to eight times larger than that in a conventional analog broadcast system in the same band width, so as to enhance a variety of services.
There is an MPEG-2 (MPEG stands for Moving Picture Expert Group) as a typical high efficiency coding system. The MPEG-2 is a coding standard which has been fostered standardization as the ISO/IEC 13818 which is the JTC (Joint Technical Committee) of the ISO (International Organization for Standardization) and the IEC (International Electro-Technical Commission).
MPEG-2 defines not only the coding, but also the multiplexing of the video or the audio data streams in order to make use of data streams of encoded video and/or audio data for a wide range of applications. This standard is called the MPEG-2 standard, and there are two kinds according to the use of data stream, i.e., the transport stream (TS: Transport Stream) for the broadcast and communicating, and the program stream (PS: Program Stream) for the storing and recording.
The transport stream is considered to transmit a plurality of programs in one stream, which will be supplied to many broadcast or communicating in the future.
On the other hand, it has been possible to decode the MPEG compression video image signal in the DSP (Digital Signal Processor). Since the processing faculty of the hardware in the DSP or the IC motion speed are improved, it is also possible to decode a plurality of video image signals or audio signals contained in the MPEG streams.
In the digital broadcast system, at the transmitter side, a plurality of MPEG-encoded video image data (TS packets) are multiplexed into one transport system, and the transport stream and other transport streams generated in the similar manner are transmitted to the transponder such as the satellite by carrier waved with different frequencies, and in receivers a plurality of transport streams which are transmitted in conjunction with carrier waves with the different frequencies are decoded in the decoder different for each frequency (containing the tuner), and from each decoded transport stream one selected video image data is MPEG-decoded, so that the decoded video image signals are displayed on the multiple screen of the display device such as the cathode lay tube (CRT), or a MPEG-decoded video images are displayed on different display devices.
When such a digital TV broadcast is received, in order to make it simple for viewer to select a desired channel, the video image signals in a plurality of channels are decoded simultaneously, a TV screen is divided into a plurality of small screens, so as to provide the multi screen display function to display these decoded channel video image signals on the respective small screens simultaneously.
That is, it is assumed that the MPEG transport system in which a plural channel of encoded TV signals are multiplexed is received, and each channels is simultaneously decoded and the combined together so as to be displayed in multi-windows on a TV screen. In this case, as shown in FIG. 1, the transport stream is demultiplexed into each TV channels in a demultiplexer (DEMUX) 101, then each of the TV channels are stored in each of the input buffer memories 201 through 204.
Here the circuit of FIG. 1 represents a related art imagined by Inventors for reference purposes to make the understanding of the present invention as described later easy, wherein a plurality of basic low circuits each comprised of one conventional decoder are coupled in parallel. Then, these video image signal streams are decoded separately in the decoders 115 through 118, and each of the decoded video image signals is stored in each of the output buffer memories 205 through 208.
Then, as shown in FIG. 2, the video signal in each channel is decoded according to the decode starting information contained in the video image signal stream in each channel. Further, in these video image signal streams to be decoded a video image signal to be assigned to a master video image signal is selected, and the decoded video image signals stored in the output buffer memories 205 through 208 are read out by the use of a synchronizing signal reproduced from the data which are used when the video signal assigned to the master video image signal is displayed, then these decoded video image signals are displayed on one screen after synchronized with each other in a synchronizer 119.
However in the conventional apparatus mentioned above, in order to match the Synchronization for combining the decoded video image signals the output buffer memory for storing the decoded video image signal is required.
Further, through the use of that of the video image signal to be assigned to a master video image signal for the vertical synchronizing signal of the display, the synchronizing signal is changed every when the mater is changed, as shown in FIG. 2, so that the phase of the vertical synchronizing signal is also changed simultaneously. Accordingly there had been a problem that the displayed video image is disturbed at the master changing time.
FIG. 3 is a block diagram showing the conventional MPEG decoder for processing a plurality of video image data. Here, it will be explained that the two video image data selected from each two transport streams are supplied to each first and the second video decoders 10 and 20 as the two input streams. The two input streams are supplied to the input terminals 11 and 21 of the first and the second video decoders, respectively. The video streams supplied to the input terminals 11 and 21 are supplied to the MPEG decoders 12 and 22 inside the first and the second video decoders so as to output the MPEG-decoded video image signals to the output terminals 13 and 23.
To the MPEG decoders 12 and 22, the clock counting values from the STC counters 15 and 25 (STC stands for the System Time Clock meaning the reference synchronizing signal), and the synchronizing signals from the synchronizing signal generators 18 and 28 based on the clock counting value are supplied.
In the PCR detectors 14 and 24 the PCR (Program Clock Reference: the program time reference value) which are the reference time information of the video image signals are extracted from each streams supplied to the input terminals 11 and 21. Each video decoders 10 and 20 are provided with each separated generators 17 and 27. Here, the PCR is contained in the input stream at a specific cycle (for instance, the cycle of 100 ms), which is used for setting or correcting the counts of the STC counters 15 and 25 to the desired counts intended at the MPEG encoder side by periodically comparing and consulting with the PCR.
The clock generated in the clock generator 17 inside the first video decoder 10 is counted in the STC counter 15. In the comparator 16, the PCR extracted from the first input stream in the PCR detector 14 and the count of the STC counter 15 are compared. Here, in the case that the difference between the values is relatively large the current PCR is loaded to the STC counter 15. While in the case that the difference is relatively small the frequency offset of the clock is detected from the difference information and the frequency is corrected to the clock generator 17.
The clock generated in the clock generator 27 inside the second video decoder 20 is counted in the STC counter 25. In the comparator 26, the PCR extracted from the second input stream in the PCR detector 24 and the count of the STC counter 25 are compared. Here, in the case that the difference between the counts is relatively large the PCR is loaded to the STC counter 25, and the in the case that the difference is relatively small the frequency offset of the clock is detected from the difference information and the frequency is corrected to the clock generator 27.
Accordingly, since the clock generators 17 and 27 oscillate at the frequency depending on the two input video streams, the MPEG decoding systems are operated by two clocks.
By the way, in the MPEG decoder, in the case of performing the video image signal processing in the DSP, the two video image data are possible to be processed in one DSP if it is a high speed type one, however, since one DSP is operated by one clock its processing is hard. Further, since the circuit systems operated by two clocks are not operated by the one clock it is hard to set up the controller, and since the distribution of the clock is fixed at the setup timing of each circuit the system with less flexibility.
It is, therefore, the present invention has an object to remove the drawbacks in the conventional apparatus and provide a video image signal decoding method and apparatus for preventing the disturbance of the displayed video image when a master video image is interchanged among a plurality of video images simultaneously displayed on the screen.
Further, the present inventions has another object to provide a video image signal decoding method and apparatus for eliminating output buffer memories used for controlling video image signals and for reducing the amount of hardware in the video image signal decoder.
So, the present invention provides a decoder for performing a plurality of decode processings by one clock, so as to make the system set up easy.
In order to achieve the above object, a video image signal decoding method according to the first aspect of the present invention includes the steps of a first step for separating at least one of streams of video image signal to be decoded from a multiplexed stream received therein, which contains a plurality of video image signals, a second step for selecting one stream including a video image signal to be assigned to a master video image signal, which will be assigned to a master stream from the multiplexed stream, a third step for regenerating a reference time and a system clock which are used in decoding of the video signal to assigned to the master video image signal, based on a reference time information contained in the master stream, a fourth step for regenerating a reference time used for decoding the separated video image signal through the use of the reference time information contained in the separated stream of the video image signal to be decoded and the regenerated system clock, a fifth step for generating a decode starting signal through the use of the regenerated system clock, a sixth step for storing the video image signal contained in the separated stream in an input buffer memory, in parallel with the processing of the steps 2 through 5, and a seventh step for starting a decoding of the video image signal stored in the input buffer memory by the decode starting signal.
A decoder according to the first aspect of the present invention includes a separator for separating at least one of streams of video image signal to be decoded from a multiplexed stream received therein, which contains a plurality of video image signal, a selector for selecting one stream including a video image signal to be assigned to a master video image signal, which will be assigned to a master stream from the multiplexed stream, at least one buffer memory for storing the video image signal contained in each separated stream, a clock regenerator for regenerating a reference time and a system clock which are used in decoding of the video image signal to assigned to the master video image signal, based on a reference time information contained in the master stream, a reference time regenerator for regenerating a reference time used for decoding the separated video image signal through the use of the reference time information contained in the stream of the video image signal to be decoded and the regenerated system clock, a decode starting signal generator for generating a decode starting signal which is common to each of the separated stream through the use of the regenerated system clock, and at least one decoder for starting a decoding of the video image signal stored in the input buffer memory by the decode starting signal.
Further in the first aspect of the present invention, the decode starting signal is a signal synchronized with a synchronizing signal in a display system which is not depend upon the decode starting time information contained in the video image signal to be assigned to a master video image signal.
Furthermore in the first aspect of the present invention, the capacity secured as the input buffer memory must be larger more than the maximum data amount supplied for one frame period of the video image signal assigned to the marker video image than the data amount required for starting decoding based on the decode starting time information contained in the data.
According to the first aspect of the present invention, since at least one stream to be decoded separated from the multiplexed stream, that the streams containing the encoded video image signal are multiplexed, are stored in each of the input buffer memories, and the video image signal are decoded in each decoders which correspond to the input buffer memories by the common decode starting signal of each streams, the timings of the video image signal output from each decoders are matched, and the video image signal is possible to be combined into one screen in the combiner directly without using of output buffer memories.
Further, since the phase of the synchronizing signal is not disturbed even the stream of the video image signal to be assigned to a master video image signal is interchanged it is possible to prevent the disturbance of the displayed video image at the master changing time.
According to the second aspect of the present invention, a decode processor configured to decode a stream of MPEG-encoded video image data transmitted to conjunction with reference time information includes a reference time information detector for detecting the reference time information contained in the stream, a clock generator for generating a clock having a frequency which is not locked to a clock in a transmitter for transmitting the stream, a counter for counting the clock from the clock generator, which count is amended by the direction from the reference time information detector, a synchronizing signal generator for generating a synchronizing signal based on the count of the counter, and a decoder for decoding the stream according to the count of the counter.
According to the second aspect of the present invention, when two video image data having each reference time information for instance are decoded in the first and the second video decoders the decode processor according to the second aspect of the present invention is used at least for the first video decoder, so that it is possible to decode one clock from the clock generator in the first and the second video decoders in common. This is, on one hand, the clock from the clock generator is used as that of the second decoder, on the other hand, when the clock from the clock generator is used by counted in the counter of the first video decoder the counting value is corrected by the detected value from the reference video information detector inside the first video decoder. That is, it is possible to provide the system capable of decoding the one clock non-synchronized with a plurality of video decoders.